Motorola 6809 microprocessor architectureMemoryProgram, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. Program memory - program can be located anywhere in memory. Jump, subroutine calls and conditional branches instructions can be used to jump anywhere in memory. Data memory - data can be anywhere in memory space. Stack memory - user and system stacks can be placed anywhere in memory space. Stacks grow downwards. Reserved memory locations:
InterruptsIRQ - maskable interrupt. When the interrupt occurs the CPU sets E condition flag, pushes program counter, index registers, accumulators and condition code register into the stack, disables further IRQ interrupts by setting I condition flag, and jumps to memory location, address of which is stored in memory FFF8h - FFF9h. To return from the interrupt the processing routine should use RTI instruction. This interrupt can be enabled/disabled by setting/clearing I condition flag. FIRQ - fast maskable interrupt. When the interrupt occurs the CPU clears E condition flag, pushes program counter and condition code register into the system stack, disables further fast and normal interrupts by setting I and F condition flags, and jumps to memory location, address of which is stored in memory FFF6h - FFF7h. To return from the interrupt the processing routine should use RTI instruction. This interrupt can be enabled/disabled by setting/clearing F condition flag. FIRQ interrupt has higher priority than IRQ. NMI - non-maskable interrupt. When the interrupt occurs the CPU clears E condition flag, pushes program counter, index registers, accumulators and condition code register into the system stack, disables further maskable interrupts by setting F and I condition flags, and jumps to memory location, address of which is stored in memory FFFCh - FFFDh. To return from the interrupt the processing routine should use RTI instruction. NMI interrupt has higher priority than IRQ and FIRQ interrupts. This interrupt can not be disabled. SWI - software interrupt. This interrupt can be only invoked from the program. When the interrupt is invoked the CPU sets E condition flag, pushes program counter, index registers, accumulators and condition code register into the system stack, disables maskable interrupts by setting F and I condition flags, and jumps to memory location, address of which is stored in memory FFFAh - FFFBh. To return from the interrupt the processing routine should use RTI instruction. SWI2 - software interrupt 2. This interrupt can be only invoked from the program. When the interrupt is invoked the CPU sets E condition flag, pushes program counter, index registers, accumulators and condition code register into the system stack, and jumps to memory location, address of which is stored in memory FFF4h - FFF5h. To return from the interrupt the processing routine should use RTI instruction. SWI3 - software interrupt 3. This interrupt works almost like SWI2 with the only exception that the address of SWI3 interrupt processing routine is located at FFF2h - FFF3h. I/O portsNone. RegistersAccumulator A (A) is an 8-bit register used for arithmetic and logical operations. Accumulator B (A) is an 8-bit register used for arithmetic and logical operations. Most instructions that work with the accumulator A can be used with the accumulator B. The only exceptions are instructions DAA (works with the accumulator A only) and ABX (works with the accumulator B only). Accumulators A and B can be combined together into 16-bit accumulator D. The register A contains the most significant byte of the accumulator D, and the register B contains the least significant byte. Index registers X and Y are a 16-bit registers that usually contain an index used for indexed addressing modes. Program counter (PC) is a 16-bit register pointing to the next instruction that will be executed by the CPU. PC register can be used with some indexed addressing modes. System stack pointer (S) is a 16-bit register pointing to the top of system stack. The system stack stores machine state during subroutine calls and interrupts. User stack pointer (U) is a 16-bit register pointing to the top of user stack. The user stack is usually used to pass arguments to/from subroutines, and it can also be used for temporary data storage. When data is pushed into the system or user stack, a stack register is decremented by 2 and then data is stored into memory location referenced by the stack pointer. Both S and U stack registers can be used as index registers. Direct Page register contains the most significant byte of the zero page address. After CPU reset this register is set to value 00h. Condition code register contains the following flags:
Instruction Set6800 instruction set consists of 59 instructions:
Addressing modesInherent - the data value/data address is implicitly associated with the instruction. Immediate - 8-bit or 16-bit data is provided in the instruction. Register - references the data in a register or in a register pair. Direct - one-byte operand provided in the instruction specifies the memory address in page zero where data is located. Page zero after processor reset always points to 0000h. Zero page address can be changed to any 256-bit page boundary by setting Direct Page register to the high order byte of the page address. For example, to move zero page to memory 8100h the Direct Page register should be set to 81h. Extended - two-byte operand provided in the instruction specifies memory location where data is stored. Extended Indirect - two-byte operand provided in the instruction specifies memory location where data address is stored. Relative - one- or two-byte offset is added to the program counter. The resulting value is a memory address containing data or memory address where the CPU transfers control. Relative Indirect - one- or two-byte offset is added to the program counter. The resulting value is a memory address where data address is stored. Indexed - the contents of one of index or pointer registers is added to fixed offset value / content of accumulator register. The resulting value is a memory address where data resides. For indirect indexed modes the calculated address points to memory where data address is stored. The processor supports the following indexed addressing modes:
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